Fast, novel, cascadable design for multi-layer networks
Tombs J., Tarassenko L.
A novel pulse-stream neural network chip has been described. Unlike many other analogue designs, it makes use of both parallel computations, and fast analogue procesing for an efficient hardware implementation. For a chip of 10,000 synapses and a master clock of 1MHz, over 1010 operations/sec are possible. It is hoped that further work on this design will lead to on-chip learning, using an algorithm under development for implementation in VLSI.